1. Field of the Invention
The present invention relates to an input overvoltage protection circuit to protect a system from an excessive input voltage, in particular to a method for implementing a soft-start function by using a component(s) of a low withstand voltage.
2. Description of Related Art
To protect a system from an excessive input voltage, overvoltage protection circuits are incorporated into input circuits. Note that such overvoltage protection circuits need to be composed of a circuit(s) having a withstand voltage capable of withstanding a conceivably highest overvoltage input. Further, in order to reduce the load on the input side that is exerted when a switch inserted between the input and the system is turned on, it has become necessary to implement certain control to suppress the inrush current to the system. Japanese Unexamined Patent Application Publication No. 2008-182802, for example, discloses such an overvoltage protection circuit.
FIG. 12 shows an overvoltage protection circuit as related art. The overvoltage protection circuit includes a PMOS transistor Q1 to separate a system 22 from an input circuit 21, voltage-dividing resistors R1 and R2 to monitor an input voltage VIN, a comparator 11 to determine the overvoltage of the input voltage VIN, voltage-dividing resistors R3, R4 and R5 to generate a comparison reference voltage, an input resistor RIN, and a clamp circuit 12. Further, an input-side bypass capacitor CIN is disposed between the input circuit 21 and the voltage-dividing resistors R1 and R2, and an output-side bypass capacitor COUT is disposed between the PMOS transistor Q1 and the system 22.
Note that the comparator 11, the clamp circuit 12, the voltage-dividing resistors R3, R4 and R5 are integrated and constructed as an LSI (large-Scale Integrated) circuit. Further, a clamping voltage VC, which is a constant voltage output, is generated by using the clamp circuit 12 and the input resistor RIN and is used as the reference voltage of the comparator 11.
With the configuration like this, when it is detected that the input voltage VIN becomes an overvoltage in an overvoltage decision by the comparator 11, the PMOS transistor Q1 is turned off. In this way, the overvoltage is not applied to the system 22. Further, when it is determined that the input voltage VIN does not exceed the overvoltage in an overvoltage decision by the comparator 11, the PMOS transistor Q1 is turned on and the voltage is supplied to the system 22.
FIG. 13 shows a timing chart of this operation. FIG. 13 shows a potential relation of a direct-current fashion among the potential of the input voltage VIN, the gate voltage VG of the PMOS transistor Q1, and the output voltage VOUT. When the input voltage VIN gradually rises and reaches the operation start voltage at a time TOO, the comparator 11 brings the gate voltage VG of the PMOS transistor Q1 to a Low level to turn on the PMOS transistor Q1. As a result, the PMOS transistor Q1 is turned on, and the output voltage VOUT is thereby supplied to the system 22. Further, if the input voltage VIN rises excessively and the comparator 11 thereby detects an overvoltage at a time T01, the comparator 11 brings the gate voltage VG of the PMOS transistor Q1 to a High level to turn off the PMOS transistor Q1. As a result, the PMOS transistor Q1 is turned off, and the voltage supply to the system 22 is stopped.
Note that in the overvoltage protection circuit shown in FIG. 12, the circuit on the LSI side can be constructed by using components of a withstand voltage lower than the input voltage VIN by interposing the clamp circuit 12.